The invention relates to ATM network node equipment and more particular to a serial/parallel high speed bus designed to transfer ATM cells between adapters.
A telecommunication equipment is generally made of adapters plugged into a switching card, each adapter interfacing ATM network links.
FIG. 1A shows the architecture of such a telecommunication equipment.
All the adapters (10-1, . . . , 10-N) are connected to a switching card (12) which controls the cells transmission. The switching card is usually based on switching components such as the IBM PRIZMA chip.
Busses in the state of the art such as ISA (Industry Standard Architecture), MCA (Micro Channel Architecture) and PCI (Peripheral Control Interface) are made of a data bus, an address bus, a read/write signal and additional control lines. These signals are activated at certain period of time depending on the mode operations that are the bus request mode, the bus acknowledge mode, the address mode, the read/write mode and the bus release mode.
It is an object of the invention to simplify the ATM switching card by implementing an ATM cell serial/parallel bus that contains a data bus, two control signals and an adapter identification bus. The data bus has different actions depending on the mode operations. There is no need for additional signals such as address bus, read/write signals, etc.
It is another object of the invention to make possible the improvement of the performance of the ATM cell bus by increasing the clock frequency or the bus width.
The ATM bus (100) is composed of a clock signal, CLK, a synchronization signal, -SYNC, and a data bus, S(0-31). It is a synchronous bus running at any clock rates. The clock signal is generated by the backplane (20) and transmitted to each adapter (10-1, . . . 10-N).
During each clock cycle, the data bus has three serialized operation modes (or cycles) defined in this order: a bus_req cycle of 1 clock period, a bus_ack cycle of 1 clock period and an ATM cell_xfr cycle of 14 clock periods.
The free-running synchronization signal is generated on the backplane (20) and transmitted to each adapter (10-1, . . . , 10-N). The activation of the synchronization signal starts the bus_req cycle. To increase the bus performance, the synchronization signal is held active until an adapter activates its bus_request signal on one bit of its data bus S(0-31). The remaining data bus signals are left in high impedance state.
For the bus_ack cycle, an arbiter located in a control logic (102) on the backplane (20), determines which adapter has the bus granted for its data transfer by generating an acknowledge signal to the corresponding requester during one clock period following the deactivation of the synchronization signal.
The next fourteen clock periods starts the xfer_cycle for transferring one ATM cell from a requester adapter to a destination adapter. At the end of this transmission, another req_cycle starts by the activation of the synchronization signal.
The high speed ATM bus according to present invention is used in an ATM network node equipment for transferring ATM cells between a plurality of connected adapters, said ATM bus comprising a clock signal (CLK), a synchronization signal (SYNC), an adapter identification bus (SID) and a data bus (S(0-31)). Responsive to said clock signal (CLK) and to said synchronization signal, it behaves as an ATM cell serial/parallel bus so as to perform three operation modes on said data bus (S(0-31)):
a bus_request operation mode;
a bus acknowledge operation mode; and
an ATM cell transfer operation mode from a first adapter to a second adapter.
Furthermore, the ATM bus is associated to means for determining the current operation mode of the ATM bus so as to ask the adapters to take appropriate actions.
According to the present invention, the method for transferring ATM cells between a plurality of connected adapters through a high speed ATM cell serial/parallel bus in an ATM network node equipment, said ATM bus comprising a clock signal (CLK), a synchronization signal (SYNC), an adapter identification bus (SID) and a data bus (S(0-31)); responsive to each of said clock cycle (CLK) and to said synchronization signal so as to perform successively said three operation modes on the data bus (S(0-31)), said method comprises the steps of:
requesting said ATM bus;
acknowledging said ATM bus; and
transferring ATM cells from a first adapter to a second adapter through said ATM bus.